Simplified analog computer and simulator having synchronously switched input and output to effect time-sharing



June 25. 1968 TAKEQ MlURA ET AL 3,390,258

SIMPLIFIED ANALOG COMPUTER AND SIMULATOR HAVING SYNCHRONOUSLY swncmsnINPUT AND OUTPUT TO EFFECT TIME-SHARING Filed May 12. 1964 aSheets-Sheet 1 F l G. l

FUNCTION GENERATOR o MULTIPLIER FUNCTiON F GENERATOR ADDER l l INTEGATORT| JIG| II l l June 25. I968 TAKEO MIURA ET AL 3,390,258

SIMPLIFIED ANALOG COMPUTER AND SIMULATOR HAVING SYNCHRONOUSLY SWITCHEDINPUT AND OUTPUT TO EFFECT TIME-SHARING Filed May 12, 1964 FIG.2

3 Sheets-Sheet 2 H| l e II T! 1 COMPUTING CIR$CUIT MULTIPLIER FUNCTIOhGENERATOR ADDER NC l I}- O I J FUNTlON GENERATOR June 25. 1968 TAKEOMIURA ET AL 3,390,258

SIMPLIFIED ANALOG COMPUTER AND SIMULATOR HAVING SYNCHRONOUSLY SWITCHEDINPUT AND OUTPUT TO EFFECT TIME-SHARING Filed May 12, 1964 5Sheets-Sheet s FIG.4

INPUT OPERATIONAL AMPLIFIER POTENTIOMETER I I. L

POTENTIOMETER SC SLi'L K(t+% u- FIG.?

SI CHANGER United States Patent 3,390,258 SIMPLIFIED ANALOG COMPUTER ANDSIMULA- TC'R HAVING SYNCHRONOUSLY SWITCHED IN PUT AND OUTPUT T0 EFFECTTIME-SHARING Takeo Miura, Tokyo-to, and Janzo Iwata, Kodaira-shi,

Japan, assignors to Kabushiki Kaisha Hitachi Seisakusho, Tokyo-to,Japan, and Hitachi Denshi Kabushiki Kaisha, Kodaire-shi, Japan, bothjoint-stock companies of Japan Filed May 12, I964, Ser. No. 366,746Claims priority, application Japan, May 15, 1963, 38/ 24,164 3 Claims.(Cl. 235-184) ABSTRACT OF THE DISCLOSURE A time-shared analog computerand simulator for compensation of errors due to dead time arising fromtimesharing, which utilizes a computing element commonly used for aplurality of channels, change-over switches for scanning the input andoutput of the computing element, a plurality of holding circuits to holdthe respective channel outputs of the computing element, and a pluralityof compensating circuits to compensate dead time subsantiallycorresponding to the quantity represented by ib-ill wherein 1' denotesthe dead time required for computation, T denotes the scanning period,and T n represents the time interval during which each of said holdingcircuits is connected to the output of said computing element andcorrectly follows up variations in the output of said computing elementas well as variations in the output of said computing element within onecyclic period.

This invention relates to analog computers, and more particularly itrelates to a new time-shared analog computer and simulator in which thecircuit arrangement is simplified by utilization of a time-sharingmethod, and in which errors arising from time-sharing are greatlyreduced.

In the case when a computer setup is to be composed of analog computersor in the case when a simulator for a special objective system is to beconstructed, a large number of computer setups of equal input and outputcharacteristics are often included in the computer setups. One exampleis the case wherein partial differential equations are solved bytransforming them into difference equations; another example is the casewherein, in a system to be simulated, there is a large number ofelements having the same characteristics.

It is an object of the present invention to provide a time-shared analogcomputer and simulator wherein, in the case where there are a largenumber of parts-having the same input and output characteristics amongcomputer setups as described above, only one of such parts is provided,its input and output are switched synchronously to effect time sharing,and, moreover, the errors arising from this time-sharing method arecompensated for to obtain more correct computation solutions.

The specific nature, principle, and details of the invention will bemore clearly apparent by reference to the following description, takenin conjunction with the accompanying drawings in which like parts aredesignated by like reference characters, and in which:

FIG. 1 is a block diagram representing one example of an ordinarycomputer setup taken as an object to be studied in the presentinvention;

FIG. 2 is a block diagram indicating a circuit obtained Patented June25, 1968 by forming the computer setup shown in FIG. 1 by a conventionaltime-sharing method;

FIG. 3 is a block diagram indicating the details of one part of thecircuit shown in FIG. 2;

FIG. 4 is graphical representation of an input waveform;

FIG. 5 is an enlargement of one part of the representation in FIG. 4;and

FIGS. 6 and 7 are schematic diagrams respectively showing the essentialparts of embodiments of the invention.

One example of an ordinary computer setup to be taken as an objectivesystem in the present invention is shown in FIG. 1. In this arrangementthere are provided adders A A A integrators I I 1,, function generatorsF0, F1, F2, and G0, G1, G2, G3, the functions to be set of the F groupand the G group being respectively equal, and multipliers M M M M M Thecircuit receives an input e and the integrators produce outputs T T Thiscomputer setup illustrates one example wherein a certain partialdifferential equation is being solved by transformation into adiiference equation and, as can be observed from FIG. 1, requires alarge number of nonlinear elements.

The solutions for the differential equations of the abovementionedrespective operational elements as well as combination thereof aredescribed in a reference book such as, for example, Electronic AnalogComputors (D-C Analog Computors) by Granino A. Korn and Theresa M. Korn,published by McGraw-Hill Book Company, Inc., 1956. At page 13 of thisbook, there is described an example of an adder; at page 17, anintegrator; and, at pages 251340, a multiplier and a function generator.

FIG. 2 illustrates one example of the case where this circuit of FIG. 1is arranged in accordance with a conventional time-shared computationsystem. In the computer setup shown in FIG. 1, there are a large numberof parts which, with the outputs T and T of contiguous integrators asinputs, carry out computations of the same form represented by thefollowing equation. The sufiix i indicates any arbitrary numericalfigure of l, 2, 3, as is frequently used for ordinary mathematicalexpres- SlOIlS i)+ i-l-l)} Accordingly, in the circuit of FIG. 2, onlyone computer setup C of the above Equation 1 is used, the input beingselected by input scanning changeover switches R and R the computationresults being selected in synchronism with the input side by an outputscanning changeover switch R and the selected outputs being respectivelyheld temporarily in hold circuits H H H Such hold circuit willsufficiently serve the purpose by use of known memory circuitsutilizing, for example, a capacitor, etc., or the circuit as shown anddescribed in FIG. 7.3 and page 347 of the abovementioned reference bookby Korn and Korn. While the outputs of the computer setup C are beingapplied to the other channels, the hold circuit H, (where i: l, 2, 3,holds the value immediately prior to the changeover to the succeedingchannel. The computer setup of the part C is shown in greater detail inFIG. 3.

If, in a time-shared computer setup of this type, the changeover speedsof the switches are caused to be amply high with respect to thecomputation frequency, solutions equivalent to those in the case where alarge number of computer sets up are provided in parallel as shown inFIG. 1 can be obtained. In this case, however, an error is introduced.More specifically, if the input of a certain one integrator (that is, anoutput resulting from timeshared computation) is considered, it is foundthat, when an input as represented by the dotted line 1 in FIG. 4 shouldbe obtained as the correct input, an input of the form represented bythe full-line curve 2 is actually introduced. As a result, theintegrator output is also caused to contain a small amount of error.Since this erroneous integrator output is returned to the input side tocarry out computation, the error accumulates, and correct computationresult cannot be obtained.

In order to decrease this error, one possibility is to increase theswitching frequency, but this frequency, being limited by the frequencycharacteristic of the computer setup C, cannot be increased above acertain level.

The present invention contemplates the provision of compensation meanswhereby the above described drawback is eliminated, and correctsolutions can be obtained even with relatively slow switching periods.

Referring to FIG. 4, when an input of staircase waveform as shown by thefull-line curve 2 enters an integrator, the effect of this input on theintegrator output is approximately equal to that in the case when aninput as indicated by the chain-line curve 3, which is the result oftaking the mean of the curve 2 to produce a smooth curve, is introduced.This equivalent, chain-line input curve 3 may be obtained, as indicatedin the enlarged representation in FIG. 5, by making the areas of thetrapezoid eabf and the triangle fcg equal.

Therefore, as is apparent from FIG. 5, the triangle fcg is equal toAedf-Aadb, and, moreover, since these two triangles edf and adb are likefigures, the respective areas thereof are proportional to the square ofthe respective sides. Accordingly, the following equation isestablished.

On the other hand, from FIG 5,

When Equation 2 is substituted for the above Equa- Where:

T is the time for one cycle of switching; and T/n is the computationtime allotted to one channel.

That is, the actual output is substantially equal to the output in thecase when the input is one which is delayed by T 1 2 ni verting ananalog input from input scanning switches R and R into a digital signal,using this digital signal to carry out computation by digital technique,and converting the digital computation result so obtained into an analogsignal as the output. In this case, the result obtained is delayed byngngy which includes the above mentioned dead time component "r.

In such a case when there is a dead time, the time T it sometimesbecomes short, and the time during which the correct value is producedis only an instant, that is, n= o. In such cases, also, the resultaccording to the above consideration is valid.

The present invention, in one of its aspects, is based on theobservation that, in the case of time-shared computation by the holdmethod as described above, an equivalent dead time equal to occurs, andthe invention provides a computer setup having means to compensate forthis dead time and thereby to produce correct solutions.

FIG. 6 shows one embodiment of the invention illustrating the methodemployed in the frequently occurring case wherein, as indicated in FIG.2, computation results produced by time-sharing in the above describedmanner become the inputs of integrators. The abovementionedpotentiometer, sign changer, etc. to be used for the purpose can bethose as described in the aforementioned literature. From the fact that,in the case where the input of an integrator I, (i.e., the output ofhold circuit H is obtained by time-shared computation, a dead time asdescribed above occurs, the input in this case expressed in the form ofa Laplace transformation e (p) may be expressed by the followingequation in terms of the correct input of the integrator I, in the formof a Laplace transformation e (p).

where:

Here, if the Laplace transformation of the input at the time when thereexists no dead time T is assumed e (p), the Laplace transformation forme at the time when there exists dead time T can be expressed by e, =e(p) exp {(-T )p}. This expression is available from ordinary text booksof mathematics or automatic control such as, for example, Servomechanismand Regulating System Design, by Chestnut & Mayer, vol. 1, 1955, NewYork. Since the resulting output e (p) is subjected to an operationrepresented by k/p by the integrator (k being the multiplying factor ofthe integrator), the following equation is obtained.

is desired as the correct solution, this solution may be obtained by acomputation which eliminates the second term and other terms thereafterin the righthand side of the above equation. As one means for thispurpose, a potentiometer P is used as indicated in FIG. 6A to multiplythe input by kT and the resulting product is added to the integratoroutput through a sign changer SC. Accordingly, by such arrangement,instead of the integrator output T in FIG. 2, an output e (p) which isexpressed by the following equation can be obtained.

Since the second term which has the greatest effect on the error isthereby eliminated, the computation accuracy is greatly elevated. Inother terms, this means that the sampling period T can be substantiallyincreased without lowering the computation accuracy.

The arrangement shown in FIG. 6 further includes a sign changer SC andan adder A. In a computer setup provided with such a compensationcircuit, it is possible to consolidate the operational amplifiers into asingle amplifier OA as shown in FIG. 63. If, in the arrangement shown inFIG. 6B, the capacitors C and C are of equal capacitance, they functionas a sign changer, and the output of this integrator circuit is the sumof an integrated output of an input applied through the input resistance7 and an output of a multiple of new] due to an input applied by way ofthe potentiometer P and the capacitor C Actually, since the switchingperiod is small, the voltage division ratio of the potentiometer is toosmall under the above described condition. Therefore, a low capacitanceof the capacitor C and a high voltage division ratio of thepotentiometer P such that their product will be equal to al gn-3 areused. Particularly in the case where a capacitor such as will cause thevoltage division ratio of the potentiometer P to be equal to unity isselected, the potentiometer P may be omitted.

In the case when the output of the time-shared computation is not theinput of the integrator, i.e., when the integrator is not used, the saidoutput, itself, may be caused to lead by T For this purpose, it isnecessary to preestimate the value in the future, said value occurringafter, by T from the computation result obtained so far up to the timeunder consideration and to present this value as the output.

In one embodiment of the invention as shown in FIG. 7 for the abovepurpose, there are provided for one channel two sample hold devices Hand H When switches 8,, S and S are switched synchronously and caused tosample hold alternately for every period, the value (denoted by Ysampled immediately prior to any time under consideration and thesampled value (denoted by Y which is earlier by one period than Y areheld in the hold state in the sample hold devices. Therefore, by usingthese values, Y corresponding to said 100, which is expressed by thefollowing equation may be used for computation.

In the above expression, the quantity represents the rate of increase ofthe mean value of Y up to the time under consideration. Therefore, theproduct resulting from multiplying this quantity by T represents thequantity attained by Y by the time T in the case when Y varies at thesame rate as that up to the time under consideration, and the sum of Yadded to the said product becomes the preestimated value leading by TThis value results from an approximation by only a first-degreedifferentiation, and by a higher degree differentiation it is alsopossible to use a closer approximation.

Although the embodiments of the invention described above in conjunctionwith FIGS. 6 and 7 are each indicated for the integrator circuit of onechannel, it is to be understood that each of these embodiments areapplicable with respect to each of the integrators I 1 of the numerouschannels indicated in FIG. 2.

As indicated above, the addition of a circuit such as to cause signalsto lead by to a time-sharing computer setup has a great effect inincreasing the accuracy and in lowering the sampling period.

As described above, the circuit composition and arrangement of theanalog computer according to the present invention is substantiallysimplified by a time-sharing method.

Moreover, the error arising from the adoption of the time sharing methodis greatly reduced. Accordingly,'the present invention is highlyeffective in a wide range of practical applications.

More specifically, the present invention is highly effective inapplications to analog simulators such as, for example, a flightsimulator wherein an engine computer carries out exactly the samecomputation with only the input differing for three engines, and,moreover, is effective in applications also with respect togeneral-purpose analog computers.

It should be understood, of course, that the foregoing disclosurerelates to only preferred embodiments of the invention and that it isintended to cover all changes and modifications of the examples of theinvention herein chosen for the purposes of the disclosure, which do notconstitute departures from the spirit and scope of the invention as setforth in the appended claims.

We claim:

1. A time-shared analog computer and simulator comprising:

a computing element commonly used for a plurality of channels; firstchangeover switches for scanning the input of said computer andsimulator and supplying said input to the input of said computingelement; a plurality of holding circuits to hold the respective channeloutputs of said computing element; second changeover switches forscanning the input of Said holding circuit and supplying said output ofthe computing element to the input of the holding circuit; a pluralityof integrators to integrate the output of said holding circuit; and aplurality of potentiometers and sign changers connected to saidpotentiometers in series to add the output of the holding circuit to theoutput of the integrator, thereby compensating errors due to dead timecorresponding to the quantity represented by wherein 7' denotes the deadtime required for computation, T denotes the scanning period, and T/nrepresents the time interval during which each of said holding circuitsis connected to the output of said computing element and correctlyfollows up variations in the output of said computing element within onecyclic period.

2. A time-shared analog computer and simulator cOmprising:

a computing element commonly used for a plurality of channels; firstchange-over switches for scanning the input of said computer andsimulator and supplying said input to the input of said computingelement; a plurality of holding circuits to hold the respective channeloutputs of said computing element; second changeover switches forscanning the input of said holding circuit and supplying said output ofthe computing element to the input of the holding circuit; a pluralityof integrators to integrate the output of said holding circuit; aplurality of capacitors connected in parallel with an input resistanceof each of said integrators inserted between said output of holdingcircuit and said input of integrator, thereby compensating errors due todead time corresponding to the quantity represented by wherein '1'denotes the time required for computation, T denotes the scanningperiod, and T/n represents the time interval during which each of saidholding circuits is connected to the output of said computing elementand correctly follows up variations in the output of said computingelement within one cyclic period.

3. A time-shared analog computer and simulator comprising:

circuit and supplying said output of the computing element to the inputof the holding circuit; first supplying switches for supplying theoutput of said second changeover switches to said two holding circuitsalternately for every period; second supplying switches switchedsynchronously by said first supplying switches for supplying the outputof said two holding circuits to a computing device to compute Yexpressed by wherein Y denotes the value sampled and stored in saidholding circuit immediately prior to any time under consideration, Ydenotes the value sampled and stored in said holding circuit, which isearlier by one period of the Y thereby compensating errors due to deadtime corresponding to the quantity represented by wherein 1 denotes thedead time required for computation, T denotes the scanning period, and T/n represents the time interval during which each of said holdingcircuits is connected to the output of said computing element andcorrectly follows up variations in the output of said computing elementwithin one cyclic period.

References Cited UNITED STATES PATENTS 8/1966 Gruet 325-15051 MALCOLM A.MORRISON, Primary Examiner. J. RUGGIERO, Assistant Examiner.

